Now we form the following truth table for output c in terms of inputs a and b:
A
|
B
|
C
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
0
|
1
|
1
|
0
|
This is a NOR gate and this is the functionality to be implemented in the above shown black box.
/*
File Name : norgate.v
Design Name : NorGate
Engineer : Vipin
Function : Implements a NOR gate.
Date : 24-09-10
*/
//declaration of the module "norgate".
module NORGATE
( a, //First input to NOR
b, //Second input to NOR
c //Output of NOR
); //End of port list
//Input and output declarations:
input a;
input b;
output c;
//NOR gate - "gate1" is the gate name and first signal name is output the rest being inputs.
nor gate1(c,a,b);
//End of the verilog code.Specified by "endmodule"
endmodule
File Name : norgate.v
Design Name : NorGate
Engineer : Vipin
Function : Implements a NOR gate.
Date : 24-09-10
*/
//declaration of the module "norgate".
module NORGATE
( a, //First input to NOR
b, //Second input to NOR
c //Output of NOR
); //End of port list
//Input and output declarations:
input a;
input b;
output c;
//NOR gate - "gate1" is the gate name and first signal name is output the rest being inputs.
nor gate1(c,a,b);
//End of the verilog code.Specified by "endmodule"
endmodule
Now we will analyse this code part by part.
In Verilog the comments can be added in two ways:
1) Single line comments by " // ".
2)Multiple line comments - starts with " /* " and ends with " */ ".
The name of the black box is given after the keyword "module".In our case it is "NORGATE".
Next the inputs and output names are written inside the brackets ( ). Normally we write all the input names first and then the output names.But note that this is not a rule.Output names can be mixed with input names but for readability we generally follow the conventional way.
Once that is done we close the bracket and declare the signal names, in port list, as either input or output.
Now we can define the functionality of the black box. We use the NOR gate primitive available in Verilog for implementing the truth table given above.
Once the functionality is coded, we have to END the black box by using the "endmodule" keyword.
As far as the simplicity is concerned this is the most it can go.It cant be simpler than this. In my future articles I will give more examples explaining the other features and keywords available in Verilog.