Monday, September 6, 2010

Difference between Harvard and Von Neumann computer architectures

There are basically two types of digital computer architectures. The first one is called Von Neumann architecture and later Harvard architecture was adopted for designing digital computers.

Von Neumann Architecture:
  • It is named after the mathematician and early computer scientist John Von Neumann.
  • The computer has single storage system(memory) for storing data as well as program to be executed.
  • Processor needs two clock cycles to complete an instruction.Pipelining the instructions is not possible with this architecture.
  • In the first clock cycle the processor gets the instruction from memory and decodes it. In the next clock cycle the required data is taken from memory. For each instruction this cycle repeats and hence needs two cycles to complete an instruction.
  • This is a relatively older architecture and was replaced by Harvard architecture.
Harvard Architecture:

  •  The name is originated from "Harvard Mark I" a relay based old computer.
  • The computer has two separate memories for storing data and program.
  • Processor can complete an instruction in one cycle if appropriate pipelining strategies are implemented.
  • In the first stage of pipeline the instruction to be executed can be taken from program memory.In the second stage of pipeline data is taken from the data memory using the decoded instruction or address. 
  • Most of the modern computing architectures are based on Harvard architecture.But the number of stages in the pipeline varies from system to system.
 These are the basic differences between the two architectures.A more comprehensive list can be found here with respect to ARM class of processors.


  1. Satisfied with this answer..Need more explanation.
    thank you

  2. i'm not sure why pipelining is not allowed on Von Neumann Architecture, is this statement correct?

    1. ARM IS Von Neumann Architecture and pipelining are there.

  3. thanks for helping me , , ,
    but yet add some more poins.

  4. yeah...i got sme details about this nd i understood...thanq.but xplain y pipelining not used n von neumann,any reason for that????

  5. Program Memory - Stores Instructions.
    Data Memory - Stores Data and their corresponding addresses.

    Von Neumann Architecture - Basic Operation.
    a. Same area for Program and Data memory.
    b. No or Single Pipe-line stage.
    c. 2 clock cycles to complete the execution of an instruction.
    d. Initially, the instruction is fetched from the program memory - 1st clock cycle.
    e. Then the corresponding data is fetched from the data memory. The data address is decoded from the instruction (here the function of the instruction can also be determined) - 2nd clock cycle.

    If pipe-lining where applicable to Von Neumann architecture then wouldn't a set of instruction fetch and address decode happen in a span of a single clock cycle ? No it would not. How ?
    At the start of clock cycle 1 -
    a. Hardware performs first an instruction fetch,decodes the instruction and puts the required data address on the bus and determines the function to be performed.
    At start of clock cycle 2 -
    b. The corresponding data would be fetched based on the address that was obtained from the instruction.
    But since pipe - Lining is not applicable/possible in the Von Neumann case as per the explanation, there is no question of multiple instruction fetch and address decoding.
    The same principle can be applied to the Harvard architecture, but with pipe lining (as per the explanation) the luxury of multiple instruction fetches and address decodes becomes possible.
    Therefore is is now possible to build multiple pipeline stage capable architectures.

    Harvard Architecture - Basic Operation.
    a. Separate areas for program and data memories.
    b. Pipe-lining is possible hence an instruction decode and data fetch may be executed within the span of a single clock cycle.
    c. Initially the instruction is fetched from the program memory.
    d. The data address is then decoded along with the functionality and the data is fetched from the data memory.
    e. Pipe-lining ensures that multiple program memory and data memory accesses overlap.

    1. I don't agree to your statement. If we look at the architecture of ARM7 TDMI based processor, it's architecture is of Von-Neumann type and still has 3 stage pipe-lining implemented. You might need to review on this.