Saturday, September 25, 2010

Introduction to Verilog - a Hardware description language

   Digital systems are very complex systems and when we go down, in the abstraction level from Algorithmic level/block level to register level or gate level the complexity increases even more.The design of such systems are always a challenge to the design engineer.To aid the design process of such systems, Hardware description languages(HDL) were evolved.

   Some of the popular HDL's are VHDL,Verilog etc. In this blog I have created a separate section for Verilog which will discuss various features and HOW TO in Verilog. In another blog I have shared many tips and tricks related to VHDL programming.

   Verilog describes a digital system as a group of modules. All these modules have an interface to other modules and contain a description of its contents. A module represents a logical unit that can be described either by specifying its internal logical structure or by describing its behavior in a program-like manner. These modules are then interconnected with wires, allowing them to communicate with each other.Verilog is easy to learn compared with other HDL like VHDL, if you know at least one programming language like C.

Abstraction Levels:
   Verilog allows you to design your digital design at various abstraction levels.Suppose you have an algorithm to be implemented in the form of a digital circuit then you can easily use Verilog constructs to do the same without worrying about the underlying circuit.Similarly lower abstraction levels are also possible with Verilog.

Few important abstraction levels are given below with some explanation:
1)Behavioral Model : This is the highest level of abstraction provided by Verilog.This is very similar to a high level programming language like C. The code doesn't contain any circuit elements at this level.We are only concerned about the algorithmic flow at this level.
2)Register-Transfer Level : In this level we describe the circuit operations by the transfer of data between the registers.Generally we can say that any code which is synthesis-able is at the RTL level of abstraction.
3)Gate Level : At this level we use the fundamental and derived versions of digital gates to implement the design.We will be only using primitives like AND,OR,NOT etc in the level.This level is not generally used since the design becomes very complicated and time consuming relative to RTL and behavior level models.


  1. Which do U consider better for bigger designs: Verilog or VHDL?
    I'm Currently working with modulation schemes based on SVPWM implemented on FPGA, and I want to enroll with the better language. I have experience with VHDL but no one with Verilog.

    Thanks a lot!

  2. VHDL will be better to use because it supports complex and bigger design easily and Verilog does not support.